Radioelectronics and radioelectronic equipment manufacturing

Reversible FPGA-Based Code Sequence Generator

Authors

D. V. Havrilov
Vinnytsia National Technical University ROR
A. Yu. Volovyk
Vinnytsia National Technical University ROR
O. S. Zviahin
Vinnytsia National Technical University ROR
D. V. Yarovyi
Vinnytsia National Technical University ROR
DOI https://doi.org/10.31649/1997-9266-2019-145-4-100-106

Keywords

reverse code sequence generator excitation function determination method flexible tracking system integral chips of hard logic Altera Quartus Intel

Abstract

Code sequence generators (CSGs) are widely used in digital systems of radio engineering and communication, computer technology and automation, for storing information and performing arithmetic operations, as well as diagnosing and correcting digital device errors in their control and synchronization circles. Among various types of CSG propagation generators were pseudo-random numbers and generators with constant codes, in which the combination of zeros and units in the bits of the register remains unchanged. A sequence is called pseudorandom, if it looks like a systemic and random, although in fact it was created using a purely deterministic process known as the pseudo-random generator. Such generators are predominantly given some initial values and, with the help of certain algorithms, receive random sequences of codes from it. In this sense, pseudorandom generators can be considered as spreaders of chance. The main disadvantages of these devices include the fact that the offset is performed only to the right, which reduces the functionality.

In this article, an analysis of modern methods for generating code sequence generators and taking into account their shortcomings, the authors proposed a new schematic solution for a reversible code sequence generator, which reduces the required resource of integrated circuits, so that it is constructed on an arbitrary bit register, thus giving an opportunity to form an output a bus of any size without changing the source code at the reverse. The method of determining the excitation function for the n-bit shift register is described, and the example of calculating the 4-bit shift register is provided, which provides a return to the main work of the system. This solution allows creating flexible systems based on standard integrated circuits of hard logic. The result of the simulation of the reverse code sequence generator in the software of the Altera Quartus II CAD with the time charts of the device operation is described.

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How to Cite

[1]
“Reversible FPGA-Based Code Sequence Generator”, Вісник ВПІ, no. 4, pp. 100–106, Aug. 2019, doi: 10.31649/1997-9266-2019-145-4-100-106.

Author Biographies

D. V. Havrilov, Vinnytsia National Technical University

Cand. Sc. (Eng), Associate Professor, Associate Professor of the Chair of Radio Engineering

A. Yu. Volovyk, Vinnytsia National Technical University

Cand. Sc. (Eng), Associate Professor of the Chair of Radio Engineering

O. S. Zviahin, Vinnytsia National Technical University

Cand. Sc. (Eng.), Associate Professor of the Chair of Radio Engineering

D. V. Yarovyi, Vinnytsia National Technical University

Student of the Department of Infocommunications, Radioelectronics and Nanosystems

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