Model of Parallel Sorter for Associative Processor

Abstract

The process of sorting and selecting by key is a basic procedure in many search systems such as databases and Internet search systems. At the same time, modern computing tools require efficient methods and tools which are connected with associative information processing in the development of software and hardware. Therefore, there is a need for high-speed non-computational (associative) processing of large amounts of information, which requires appropriate organization and improvement of technical means of sorting. The well-known algorithms and means for number sorting make it possible to regulate the intensity of this process and increase its efficiency using parallel devices, but they require significant hardware costs. Therefore, the purpose of further research is to develop new and improve known methods of sorting with an orientation on reducing hardware costs and increasing the speed of this process. In this paper, there has been proposed a block diagram of a sorter as a computational part of an associative processor, which has a regular logical structure and parallel-serial connections between data processing units. This greatly simplifies the "placement" of the sorter in a programmable logic IS (FPGA) chip. In addition, the sorter functionally implements the multifunctionality of processing numerical data arrays due to the formation of the ranks of the input array of elements. This allows determining not only the extreme elements of the numeric array but also the element occupying the average value in the sorted array, which is a necessary condition for high-speed median filtering of images. In the proposed sorter, the sorting process uses fast increment/decrement operations on the counter arrays instead of the time-consuming operation of pairwise comparison in parallel for all arrays of elements with their subsequent re-commutation.