Implementation of a Two-Input Discrete Perceptron with Shifted Synaptic Signals on FPGA Using AlteraHDL

Abstract

The paper proposes and experimentally investigates a hardware implementation of a discrete two-input probabilistic perceptron on a Field-Programmable Gate Array (FPGA). The perceptron is constructed from three elementary modules — shift2b (synaptic signal shifting via simple addition), cnts (aggregation based on counting the number of unique values), and cmp2b (a two-bit activation comparator). The hardware implementation of the discrete perceptron relies on shifting input signals using an integer addition operation, which significantly reduces hardware requirements.

Additionally, the proposed perceptron architecture ensures minimal component complexity (2–3 logic elements per block) and enables, by merely altering the weights and threshold, the emulation of six basic Boolean operations — OR, AND, XOR, NOR, NAND, and XNOR. This approach enables the creation of hardware mono-structural components based on a unified block, capable of implementing different logical functions depending on application requirements.

Functional simulation confirmed the correctness of all implemented truth tables, and timing analysis indicated a critical path delay of 16.7 ns, corresponding to an operating frequency of approximately 60 MHz without pipelining. The derived analytical relations demonstrate the potential for reducing hardware resource usage compared to traditional linear adders when synthesizing first- and second-order logic functions.

The proposed approach paves the way for scaling to a higher number of inputs, integration of statistical (probabilistic) aggregation criteria, and the development of embedded on-chip learning procedures. The results confirm the viability of using discrete perceptron structures as lightweight, energy-efficient classifiers in real-time systems and specialized neural network accelerators.